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  	    :     	                                                                                                                                                                                                                                                                                                                                                                                                                                      simulator lang=spectre
//
//ENTIRE DSP CHIP
//
subckt DSPChip VDD VSS a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 s0 s1 s2 clock out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 carryOut
registerA (VDD VSS clock a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 aOut0 aOut1 aOut2 aOut3 aOut4 aOut5 aOut6 aOut7 aOut8 aOut9 aOut10 aOut11 aOut12 aOut13 aOut14 aOut15) register16Bit
invA0_0 (VDD VSS aOut0 interA0) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA0_1 (VDD VSS interA0 aIn0) ece3663Inverter wp=6*3u wn=6*1.5u
invA1_0 (VDD VSS aOut1 interA1) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA1_1 (VDD VSS interA1 aIn1) ece3663Inverter wp=6*3u wn=6*1.5u
invA2_0 (VDD VSS aOut2 interA2) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA2_1 (VDD VSS interA2 aIn2) ece3663Inverter wp=6*3u wn=6*1.5u
invA3_0 (VDD VSS aOut3 interA3) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA3_1 (VDD VSS interA3 aIn3) ece3663Inverter wp=6*3u wn=6*1.5u
invA4_0 (VDD VSS aOut4 interA4) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA4_1 (VDD VSS interA4 aIn4) ece3663Inverter wp=6*3u wn=6*1.5u
invA5_0 (VDD VSS aOut5 interA5) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA5_1 (VDD VSS interA5 aIn5) ece3663Inverter wp=6*3u wn=6*1.5u
invA6_0 (VDD VSS aOut6 interA6) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA6_1 (VDD VSS interA6 aIn6) ece3663Inverter wp=6*3u wn=6*1.5u
invA7_0 (VDD VSS aOut7 interA7) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA7_1 (VDD VSS interA7 aIn7) ece3663Inverter wp=6*3u wn=6*1.5u
invA8_0 (VDD VSS aOut8 interA8) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA8_1 (VDD VSS interA8 aIn8) ece3663Inverter wp=6*3u wn=6*1.5u
invA9_0 (VDD VSS aOut9 interA9) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA9_1 (VDD VSS interA9 aIn9) ece3663Inverter wp=6*3u wn=6*1.5u
invA10_0 (VDD VSS aOut10 interA10) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA10_1 (VDD VSS interA10 aIn10) ece3663Inverter wp=6*3u wn=6*1.5u
invA11_0 (VDD VSS aOut11 interA11) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA11_1 (VDD VSS interA11 aIn11) ece3663Inverter wp=6*3u wn=6*1.5u
invA12_0 (VDD VSS aOut12 interA12) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA12_1 (VDD VSS interA12 aIn12) ece3663Inverter wp=6*3u wn=6*1.5u
invA13_0 (VDD VSS aOut13 interA13) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA13_1 (VDD VSS interA13 aIn13) ece3663Inverter wp=6*3u wn=6*1.5u
invA14_0 (VDD VSS aOut14 interA14) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA14_1 (VDD VSS interA14 aIn14) ece3663Inverter wp=6*3u wn=6*1.5u
invA15_0 (VDD VSS aOut15 interA15) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA15_1 (VDD VSS interA15 aIn15) ece3663Inverter wp=6*3u wn=6*1.5u 
registerB (VDD VSS clock b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15) register16Bit
invB0_0 (VDD VSS bOut0 interB0) ece3663Inverter 
invB0_1 (VDD VSS interB0 bIn0) ece3663Inverter wp=2*3u wn=2*1.5u
invB1_0 (VDD VSS bOut1 interB1) ece3663Inverter
invB1_1 (VDD VSS interB1 bIn1) ece3663Inverter wp=2*3u wn=2*1.5u
invB2_0 (VDD VSS bOut2 interB2) ece3663Inverter
invB2_1 (VDD VSS interB2 bIn2) ece3663Inverter wp=2*3u wn=2*1.5u
invB3_0 (VDD VSS bOut3 interB3) ece3663Inverter
invB3_1 (VDD VSS interB3 bIn3) ece3663Inverter wp=2*3u wn=2*1.5u
invB4_0 (VDD VSS bOut4 interB4) ece3663Inverter
invB4_1 (VDD VSS interB4 bIn4) ece3663Inverter wp=2*3u wn=2*1.5u
invB5_0 (VDD VSS bOut5 interB5) ece3663Inverter
invB5_1 (VDD VSS interB5 bIn5) ece3663Inverter wp=2*3u wn=2*1.5u
invB6_0 (VDD VSS bOut6 interB6) ece3663Inverter
invB6_1 (VDD VSS interB6 bIn6) ece3663Inverter wp=2*3u wn=2*1.5u
invB7_0 (VDD VSS bOut7 interB7) ece3663Inverter
invB7_1 (VDD VSS interB7 bIn7) ece3663Inverter wp=2*3u wn=2*1.5u
invB8_0 (VDD VSS bOut8 interB8) ece3663Inverter
invB8_1 (VDD VSS interB8 bIn8) ece3663Inverter wp=2*3u wn=2*1.5u
invB9_0 (VDD VSS bOut9 interB9) ece3663Inverter
invB9_1 (VDD VSS interB9 bIn9) ece3663Inverter wp=2*3u wn=2*1.5u
invB10_0 (VDD VSS bOut10 interB10) ece3663Inverter
invB10_1 (VDD VSS interB10 bIn10) ece3663Inverter wp=2*3u wn=2*1.5u
invB11_0 (VDD VSS bOut11 interB11) ece3663Inverter
invB11_1 (VDD VSS interB11 bIn11) ece3663Inverter wp=2*3u wn=2*1.5u
invB12_0 (VDD VSS bOut12 interB12) ece3663Inverter
invB12_1 (VDD VSS interB12 bIn12) ece3663Inverter wp=2*3u wn=2*1.5u
invB13_0 (VDD VSS bOut13 interB13) ece3663Inverter
invB13_1 (VDD VSS interB13 bIn13) ece3663Inverter wp=2*3u wn=2*1.5u
invB14_0 (VDD VSS bOut14 interB14) ece3663Inverter
invB14_1 (VDD VSS interB14 bIn14) ece3663Inverter wp=2*3u wn=2*1.5u
invB15_0 (VDD VSS bOut15 interB15) ece3663Inverter
invB15_1 (VDD VSS interB15 bIn15) ece3663Inverter wp=2*3u wn=2*1.5u
implementedALU (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 s0 s1 s2 clock r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 carryOut) ALU
registerOut (VDD VSS clock r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15) register16Bit
ends DSPChip 
//
//TEST DSPCHIP
//
subckt testDSPChip VDD VSS a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 s0 s1 s2 clock out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 r0 r1 r2 r3 r4 r5 ALUout6 ALUout7 ALUout8 ALUout9 r10 r11 r12 r13 r14 r15 carryOut
registerA (VDD VSS clock a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 aOut0 aOut1 aOut2 aOut3 aOut4 aOut5 aOut6 aOut7 aOut8 aOut9 aOut10 aOut11 aOut12 aOut13 aOut14 aOut15) register16Bit
invA0_0 (VDD VSS aOut0 interA0) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA0_1 (VDD VSS interA0 aIn0) ece3663Inverter wp=6*3u wn=6*1.5u
invA1_0 (VDD VSS aOut1 interA1) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA1_1 (VDD VSS interA1 aIn1) ece3663Inverter wp=6*3u wn=6*1.5u
invA2_0 (VDD VSS aOut2 interA2) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA2_1 (VDD VSS interA2 aIn2) ece3663Inverter wp=6*3u wn=6*1.5u
invA3_0 (VDD VSS aOut3 interA3) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA3_1 (VDD VSS interA3 aIn3) ece3663Inverter wp=6*3u wn=6*1.5u
invA4_0 (VDD VSS aOut4 interA4) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA4_1 (VDD VSS interA4 aIn4) ece3663Inverter wp=6*3u wn=6*1.5u
invA5_0 (VDD VSS aOut5 interA5) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA5_1 (VDD VSS interA5 aIn5) ece3663Inverter wp=6*3u wn=6*1.5u
invA6_0 (VDD VSS aOut6 interA6) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA6_1 (VDD VSS interA6 aIn6) ece3663Inverter wp=6*3u wn=6*1.5u
invA7_0 (VDD VSS aOut7 interA7) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA7_1 (VDD VSS interA7 aIn7) ece3663Inverter wp=6*3u wn=6*1.5u
invA8_0 (VDD VSS aOut8 interA8) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA8_1 (VDD VSS interA8 aIn8) ece3663Inverter wp=6*3u wn=6*1.5u
invA9_0 (VDD VSS aOut9 interA9) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA9_1 (VDD VSS interA9 aIn9) ece3663Inverter wp=6*3u wn=6*1.5u
invA10_0 (VDD VSS aOut10 interA10) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA10_1 (VDD VSS interA10 aIn10) ece3663Inverter wp=6*3u wn=6*1.5u
invA11_0 (VDD VSS aOut11 interA11) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA11_1 (VDD VSS interA11 aIn11) ece3663Inverter wp=6*3u wn=6*1.5u
invA12_0 (VDD VSS aOut12 interA12) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA12_1 (VDD VSS interA12 aIn12) ece3663Inverter wp=6*3u wn=6*1.5u
invA13_0 (VDD VSS aOut13 interA13) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA13_1 (VDD VSS interA13 aIn13) ece3663Inverter wp=6*3u wn=6*1.5u
invA14_0 (VDD VSS aOut14 interA14) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA14_1 (VDD VSS interA14 aIn14) ece3663Inverter wp=6*3u wn=6*1.5u
invA15_0 (VDD VSS aOut15 interA15) ece3663Inverter wp=1.5*3u wn=1.5*1.5u
invA15_1 (VDD VSS interA15 aIn15) ece3663Inverter wp=6*3u wn=6*1.5u 
registerB (VDD VSS clock b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15) register16Bit
invB0_0 (VDD VSS bOut0 interB0) ece3663Inverter 
invB0_1 (VDD VSS interB0 bIn0) ece3663Inverter wp=2*3u wn=2*1.5u
invB1_0 (VDD VSS bOut1 interB1) ece3663Inverter
invB1_1 (VDD VSS interB1 bIn1) ece3663Inverter wp=2*3u wn=2*1.5u
invB2_0 (VDD VSS bOut2 interB2) ece3663Inverter
invB2_1 (VDD VSS interB2 bIn2) ece3663Inverter wp=2*3u wn=2*1.5u
invB3_0 (VDD VSS bOut3 interB3) ece3663Inverter
invB3_1 (VDD VSS interB3 bIn3) ece3663Inverter wp=2*3u wn=2*1.5u
invB4_0 (VDD VSS bOut4 interB4) ece3663Inverter
invB4_1 (VDD VSS interB4 bIn4) ece3663Inverter wp=2*3u wn=2*1.5u
invB5_0 (VDD VSS bOut5 interB5) ece3663Inverter
invB5_1 (VDD VSS interB5 bIn5) ece3663Inverter wp=2*3u wn=2*1.5u
invB6_0 (VDD VSS bOut6 interB6) ece3663Inverter
invB6_1 (VDD VSS interB6 bIn6) ece3663Inverter wp=2*3u wn=2*1.5u
invB7_0 (VDD VSS bOut7 interB7) ece3663Inverter
invB7_1 (VDD VSS interB7 bIn7) ece3663Inverter wp=2*3u wn=2*1.5u
invB8_0 (VDD VSS bOut8 interB8) ece3663Inverter
invB8_1 (VDD VSS interB8 bIn8) ece3663Inverter wp=2*3u wn=2*1.5u
invB9_0 (VDD VSS bOut9 interB9) ece3663Inverter
invB9_1 (VDD VSS interB9 bIn9) ece3663Inverter wp=2*3u wn=2*1.5u
invB10_0 (VDD VSS bOut10 interB10) ece3663Inverter
invB10_1 (VDD VSS interB10 bIn10) ece3663Inverter wp=2*3u wn=2*1.5u
invB11_0 (VDD VSS bOut11 interB11) ece3663Inverter
invB11_1 (VDD VSS interB11 bIn11) ece3663Inverter wp=2*3u wn=2*1.5u
invB12_0 (VDD VSS bOut12 interB12) ece3663Inverter
invB12_1 (VDD VSS interB12 bIn12) ece3663Inverter wp=2*3u wn=2*1.5u
invB13_0 (VDD VSS bOut13 interB13) ece3663Inverter
invB13_1 (VDD VSS interB13 bIn13) ece3663Inverter wp=2*3u wn=2*1.5u
invB14_0 (VDD VSS bOut14 interB14) ece3663Inverter
invB14_1 (VDD VSS interB14 bIn14) ece3663Inverter wp=2*3u wn=2*1.5u
invB15_0 (VDD VSS bOut15 interB15) ece3663Inverter
invB15_1 (VDD VSS interB15 bIn15) ece3663Inverter wp=2*3u wn=2*1.5u
implementedALU (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 s0 s1 s2 clock r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 carryOut) testALU
registerOut (VDD VSS clock r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15) register16Bit
ends testDSPChip 

//
//ENTIRE ALU
//
subckt ALU VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15 nop0 nop1 nop2 nop3 nop4 nop5 nop6 nop7 nop8 nop9 nop10 nop11 nop12 nop13 nop14 nop15 s0 s1 s2 clock r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 carryOut
passA (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 passAOut0 passAOut1 passAOut2 passAOut3 passAOut4 passAOut5 passAOut6 passAOut7 passAOut8 passAOut9 passAOut10 passAOut11 passAOut12 passAOut13 passAOut14 passAOut15) passA16Bit
and (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15 andOut0 andOut1 andOut2 andOut3 andOut4 andOut5 andOut6 andOut7 andOut8 andOut9 andOut10 andOut11 andOut12 andOut13 andOut14 andOut15) and16Bit
or (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15 orOut0 orOut1 orOut2 orOut3 orOut4 orOut5 orOut6 orOut7 orOut8 orOut9 orOut10 orOut11 orOut12 orOut13 orOut14 orOut15) or16Bit
subAndAdd (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15 s0 s0 sumOut0 sumOut1 sumOut2 sumOut3 sumOut4 sumOut5 sumOut6 sumOut7 sumOut8 sumOut9 sumOut10 sumOut11 sumOut12 sumOut13 sumOut14 sumOut15 carryOut) subtractorAndAdder16Bit
shifter (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1  shiftOut0 shiftOut1 shiftOut2 shiftOut3 shiftOut4 shiftOut5 shiftOut6 shiftOut7 shiftOut8 shiftOut9 shiftOut10 shiftOut11 shiftOut12 shiftOut13 shiftOut14 shiftOut15) ccShifter
counter (VDD VSS s0 s1 s2 a0 a1 a2 clock countOut0 countOut1 countOut2 countOut3 countOut4 countOut5 countOut6 countOut7 countOut8 countOut9 countOut10 countOut11 countOut12 countOut13 countOut14 countOut15) fullCounter
mux7To1_0  (VDD VSS sumOut0  nop0  passAOut0  shiftOut0  andOut0  orOut0  countOut0  s0 s1 s2 r0) mux7To1
mux7To1_1  (VDD VSS sumOut1  nop1  passAOut1  shiftOut1  andOut1  orOut1  countOut1  s0 s1 s2 r1) mux7To1
mux7To1_2  (VDD VSS sumOut2  nop2  passAOut2  shiftOut2  andOut2  orOut2  countOut2  s0 s1 s2 r2) mux7To1
mux7To1_3  (VDD VSS sumOut3  nop3  passAOut3  shiftOut3  andOut3  orOut3  countOut3  s0 s1 s2 r3) mux7To1
mux7To1_4  (VDD VSS sumOut4  nop4  passAOut4  shiftOut4  andOut4  orOut4  countOut4  s0 s1 s2 r4) mux7To1
mux7To1_5  (VDD VSS sumOut5  nop5  passAOut5  shiftOut5  andOut5  orOut5  countOut5  s0 s1 s2 r5) mux7To1
mux7To1_6  (VDD VSS sumOut6  nop6  passAOut6  shiftOut6  andOut6  orOut6  countOut6  s0 s1 s2 r6) mux7To1
mux7To1_7  (VDD VSS sumOut7  nop7  passAOut7  shiftOut7  andOut7  orOut7  countOut7  s0 s1 s2 r7) mux7To1
mux7To1_8  (VDD VSS sumOut8  nop8  passAOut8  shiftOut8  andOut8  orOut8  countOut8  s0 s1 s2 r8) mux7To1
mux7To1_9  (VDD VSS sumOut9  nop9  passAOut9  shiftOut9  andOut9  orOut9  countOut9  s0 s1 s2 r9) mux7To1
mux7To1_10 (VDD VSS sumOut10 nop10 passAOut10 shiftOut10 andOut10 orOut10 countOut10 s0 s1 s2 r10) mux7To1
mux7To1_11 (VDD VSS sumOut11 nop11 passAOut11 shiftOut11 andOut11 orOut11 countOut11 s0 s1 s2 r11) mux7To1
mux7To1_12 (VDD VSS sumOut12 nop12 passAOut12 shiftOut12 andOut12 orOut12 countOut12 s0 s1 s2 r12) mux7To1
mux7To1_13 (VDD VSS sumOut13 nop13 passAOut13 shiftOut13 andOut13 orOut13 countOut13 s0 s1 s2 r13) mux7To1
mux7To1_14 (VDD VSS sumOut14 nop14 passAOut14 shiftOut14 andOut14 orOut14 countOut14 s0 s1 s2 r14) mux7To1
mux7To1_15 (VDD VSS sumOut15 nop15 passAOut15 shiftOut15 andOut15 orOut15 countOut15 s0 s1 s2 r15) mux7To1
ends ALU
//
//TEST ALU
//
subckt testALU VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15 nop0 nop1 nop2 nop3 nop4 nop5 nop6 nop7 nop8 nop9 nop10 nop11 nop12 nop13 nop14 nop15 s0 s1 s2 clock r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 carryOut
passA (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 passAOut0 passAOut1 passAOut2 passAOut3 passAOut4 passAOut5 passAOut6 passAOut7 passAOut8 passAOut9 passAOut10 passAOut11 passAOut12 passAOut13 passAOut14 passAOut15) passA16Bit
and (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15 andOut0 andOut1 andOut2 andOut3 andOut4 andOut5 andOut6 andOut7 andOut8 andOut9 andOut10 andOut11 andOut12 andOut13 andOut14 andOut15) and16Bit
or (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15 orOut0 orOut1 orOut2 orOut3 orOut4 orOut5 orOut6 orOut7 orOut8 orOut9 orOut10 orOut11 orOut12 orOut13 orOut14 orOut15) or16Bit
subAndAdd (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1 bIn2 bIn3 bIn4 bIn5 bIn6 bIn7 bIn8 bIn9 bIn10 bIn11 bIn12 bIn13 bIn14 bIn15 s0 s0 sumOut0 sumOut1 sumOut2 sumOut3 sumOut4 sumOut5 sumOut6 sumOut7 sumOut8 sumOut9 sumOut10 sumOut11 sumOut12 sumOut13 sumOut14 sumOut15 carryOut) subtractorAndAdder16Bit
shifter (VDD VSS aIn0 aIn1 aIn2 aIn3 aIn4 aIn5 aIn6 aIn7 aIn8 aIn9 aIn10 aIn11 aIn12 aIn13 aIn14 aIn15 bIn0 bIn1  shiftOut0 shiftOut1 shiftOut2 shiftOut3 shiftOut4 shiftOut5 shiftOut6 shiftOut7 shiftOut8 shiftOut9 shiftOut10 shiftOut11 shiftOut12 shiftOut13 shiftOut14 shiftOut15) ccShifter
mux7To1_0  (VDD VSS sumOut0  nop0  passAOut0  shiftOut0  andOut0  orOut0  VSS  s0 s1 s2 r0) mux7To1
mux7To1_1  (VDD VSS sumOut1  nop1  passAOut1  shiftOut1  andOut1  orOut1  VSS  s0 s1 s2 r1) mux7To1
mux7To1_2  (VDD VSS sumOut2  nop2  passAOut2  shiftOut2  andOut2  orOut2  VSS  s0 s1 s2 r2) mux7To1
mux7To1_3  (VDD VSS sumOut3  nop3  passAOut3  shiftOut3  andOut3  orOut3  VSS  s0 s1 s2 r3) mux7To1
mux7To1_4  (VDD VSS sumOut4  nop4  passAOut4  shiftOut4  andOut4  orOut4  VSS  s0 s1 s2 r4) mux7To1
mux7To1_5  (VDD VSS sumOut5  nop5  passAOut5  shiftOut5  andOut5  orOut5  VSS  s0 s1 s2 r5) mux7To1
mux7To1_6  (VDD VSS sumOut6  nop6  passAOut6  shiftOut6  andOut6  orOut6  VSS  s0 s1 s2 r6) mux7To1
mux7To1_7  (VDD VSS sumOut7  nop7  passAOut7  shiftOut7  andOut7  orOut7  VSS  s0 s1 s2 r7) mux7To1
mux7To1_8  (VDD VSS sumOut8  nop8  passAOut8  shiftOut8  andOut8  orOut8  VSS  s0 s1 s2 r8) mux7To1
mux7To1_9  (VDD VSS sumOut9  nop9  passAOut9  shiftOut9  andOut9  orOut9  VSS  s0 s1 s2 r9) mux7To1
mux7To1_10 (VDD VSS sumOut10 nop10 passAOut10 shiftOut10 andOut10 orOut10 VSS s0 s1 s2 r10) mux7To1
mux7To1_11 (VDD VSS sumOut11 nop11 passAOut11 shiftOut11 andOut11 orOut11 VSS s0 s1 s2 r11) mux7To1
mux7To1_12 (VDD VSS sumOut12 nop12 passAOut12 shiftOut12 andOut12 orOut12 VSS s0 s1 s2 r12) mux7To1
mux7To1_13 (VDD VSS sumOut13 nop13 passAOut13 shiftOut13 andOut13 orOut13 VSS s0 s1 s2 r13) mux7To1
mux7To1_14 (VDD VSS sumOut14 nop14 passAOut14 shiftOut14 andOut14 orOut14 VSS s0 s1 s2 r14) mux7To1
mux7To1_15 (VDD VSS sumOut15 nop15 passAOut15 shiftOut15 andOut15 orOut15 VSS s0 s1 s2 r15) mux7To1
ends testALU

//
//PASS A ALU FUNCTION
//
subckt passA16Bit VDD VSS a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15
pass0  (VDD VSS a0  out0)  passA1Bit
pass1  (VDD VSS a1  out1)  passA1Bit
pass2  (VDD VSS a2  out2)  passA1Bit
pass3  (VDD VSS a3  out3)  passA1Bit
pass4  (VDD VSS a4  out4)  passA1Bit
pass5  (VDD VSS a5  out5)  passA1Bit
pass6  (VDD VSS a6  out6)  passA1Bit
pass7  (VDD VSS a7  out7)  passA1Bit
pass8  (VDD VSS a8  out8)  passA1Bit
pass9  (VDD VSS a9  out9)  passA1Bit
pass10 (VDD VSS a10 out10) passA1Bit
pass11 (VDD VSS a11 out11) passA1Bit
pass12 (VDD VSS a12 out12) passA1Bit
pass13 (VDD VSS a13 out13) passA1Bit
pass14 (VDD VSS a14 out14) passA1Bit
pass15 (VDD VSS a15 out15) passA1Bit
ends passA16Bit

subckt passA1Bit VDD VSS in out 
inverter1 (VDD VSS in inter1) ece3663Inverter
inverter2 (VDD VSS inter1 out) ece3663Inverter
ends passA1Bit
//
//AND ALU FUNCTION
//
subckt and16Bit VDD VSS a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 
and0  (VDD VSS a0  b0  out0)  ece3663AND2
and1  (VDD VSS a1  b1  out1)  ece3663AND2
and2  (VDD VSS a2  b2  out2)  ece3663AND2
and3  (VDD VSS a3  b3  out3)  ece3663AND2
and4  (VDD VSS a4  b4  out4)  ece3663AND2
and5  (VDD VSS a5  b5  out5)  ece3663AND2
and6  (VDD VSS a6  b6  out6)  ece3663AND2
and7  (VDD VSS a7  b7  out7)  ece3663AND2
and8  (VDD VSS a8  b8  out8)  ece3663AND2
and9  (VDD VSS a9  b9  out9)  ece3663AND2
and10 (VDD VSS a10 b10 out10) ece3663AND2
and11 (VDD VSS a11 b11 out11) ece3663AND2
and12 (VDD VSS a12 b12 out12) ece3663AND2
and13 (VDD VSS a13 b13 out13) ece3663AND2
and14 (VDD VSS a14 b14 out14) ece3663AND2
and15 (VDD VSS a15 b15 out15) ece3663AND2
ends and16Bit
//
//OR ALU FUNCTION
//
subckt or16Bit VDD VSS a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15
or0  (VDD VSS a0  b0  out0)  ece3663OR2
or1  (VDD VSS a1  b1  out1)  ece3663OR2
or2  (VDD VSS a2  b2  out2)  ece3663OR2
or3  (VDD VSS a3  b3  out3)  ece3663OR2
or4  (VDD VSS a4  b4  out4)  ece3663OR2
or5  (VDD VSS a5  b5  out5)  ece3663OR2
or6  (VDD VSS a6  b6  out6)  ece3663OR2
or7  (VDD VSS a7  b7  out7)  ece3663OR2
or8  (VDD VSS a8  b8  out8)  ece3663OR2
or9  (VDD VSS a9  b9  out9)  ece3663OR2
or10 (VDD VSS a10 b10 out10) ece3663OR2
or11 (VDD VSS a11 b11 out11) ece3663OR2
or12 (VDD VSS a12 b12 out12) ece3663OR2
or13 (VDD VSS a13 b13 out13) ece3663OR2
or14 (VDD VSS a14 b14 out14) ece3663OR2
or15 (VDD VSS a15 b15 out15) ece3663OR2
ends or16Bit
//
//ADD AND SUB ALU FUNCTIONS
//
subckt subtractorAndAdder16Bit VDD VSS a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 cIn0 subControl sum0 sum1 sum2 sum3 sum4 sum5 sum6 sum7 sum8 sum9 sum10 sum11 sum12 sum13 sum14 sum15 cOut15
//vdd vss a's b's cin's subControl sum's cout's  
sAA2b0 (VDD VSS a0 a1 b0 b1 cIn0 subControl sum0 sum1 cOut1) subtractorAndAdder2Bit 
sAA2b1 (VDD VSS a2 a3 b2 b3 cOut1 subControl sum2 sum3 cOut3) subtractorAndAdder2Bit 
sAA2b2 (VDD VSS a4 a5 b4 b5 cOut3 subControl sum4 sum5 cOut5) subtractorAndAdder2Bit 
sAA2b3 (VDD VSS a6 a7 b6 b7 cOut5 subControl sum6 sum7 cOut7) subtractorAndAdder2Bit 
sAA2b4 (VDD VSS a8 a9 b8 b9 cOut7 subControl sum8 sum9 cOut9) subtractorAndAdder2Bit 
sAA2b5 (VDD VSS a10 a11 b11 b3 cOut9 subControl sum10 sum11 cOut11) subtractorAndAdder2Bit 
sAA2b6 (VDD VSS a12 a13 b13 b3 cOut11 subControl sum12 sum13 cOut13) subtractorAndAdder2Bit 
sAA2b7 (VDD VSS a14 a15 b15 b3 cOut13 subControl sum14 sum15 cOut15) subtractorAndAdder2Bit 
ends subtractorAndAdder16Bit

subckt subtractorAndAdder2Bit VDD VSS a0 a1 b0 b1 cIn0 subControl sum0 sum1 cOut1
inverterB0 (VDD VSS b0 bNOT0) ece3663Inverter
inverterB1 (VDD VSS b1 bNOT1) ece3663Inverter
muxB0 (VDD VSS b0 bNOT0 subControl outMUXB0) ece3663MUX2to1 
muxB1 (VDD VSS b1 bNOT1 subControl outMUXB1) ece3663MUX2to1
mirrorAdder2Bit (VDD VSS a0 a1 outMUXB0 outMUXB1 cIn0 sum0 sum1 cOut1) mirrorAdder2Bit
ends subtractorAndAdder2Bit 

subckt mirrorAdder2Bit VDD VSS a0 a1 b0 b1 cIn0 sum0 sum1 cOut1
mA1b0 (VDD VSS a0 b0 cIn0 sumNOT0 cOutNOT0) mirrorAdder1Bit
sum0Inverter (VDD VSS sumNOT0 sum0) ece3663Inverter
a1Inverter (VDD VSS a1 aNOT1) ece3663Inverter
b1Inverter (VDD VSS b1 bNOT1) ece3663Inverter
mA1b1 (VDD VSS aNOT1 bNOT1 cOutNOT0 sum1 cOut1) mirrorAdder1Bit
ends mirrorAdder2Bit

subckt mirrorAdder1Bit VDD VSS inA inB carryIn invertedSum invertedCarryOut
parameters w=1.5u wp=3u wn=1.5u ln=600n lp=600n mult=1 widthMult=1
	pKillAParallel (int1 inA vDD vDD) ami06P w=w*12 l=lp as=1.5u*w*12 ad=1.5u*w*12 ps=3u+w*12 pd=3u+w*12 m=mult region=sat
	pKillBParallel (int1 inB vDD vDD) ami06P w=w*12 l=lp as=1.5u*w*12 ad=1.5u*w*12 ps=3u+w*12 pd=3u+w*12 m=mult region=sat
	pKillCi (invertedCarryOut carryIn int1 vDD) ami06P w=w*12 l=lp  as=1.5u*w*12 ad=1.5u*w*12 ps=3u+w*12 pd=3u+w*12 m=mult region=sat
	pKillBSeries (int2 inB vDD vDD) ami06P w=w*4 l=lp as=1.5u*w*4 ad=1.5u*w*4 ps=3u+w*4 pd=3u+w*4 m=mult region=sat
	pKillASeries (invertedCarryOut inA int2 vDD) ami06P w=w*4 l=lp as=1.5u*w*4 ad=1.5u*w*4 ps=3u+w*4 pd=3u+w*4 m=mult region=sat
	nGenCi (invertedCarryOut carryIn int3 vSS) ami06N w=w*6 l=ln as=1.5u*w*6 ad=1.5u*w*6 ps=3u+w*6 pd=3u+w*6 m=mult region=sat
	nGenAParallel (int3 inA vSS vSS) ami06N w=w*6 l=ln as=1.5u*w*6 ad=1.5u*w*6 ps=3u+w*6 pd=3u+w*6 m=mult region=sat
	nGenBParallel (int3 inB vSS vSS) ami06N w=w*6 l=ln as=1.5u*w*6 ad=1.5u*w*6 ps=3u+w*6 pd=3u+w*6 m=mult region=sat
	nGenASeries (invertedCarryOut inA int4 vSS) ami06N w=w*2 l=ln as=1.5u*w*2 ad=1.5u*w*2 ps=3u+w*2 pd=3u+w*2 m=mult region=sat
	nGenBSeries (int4 inB vSS vSS) ami06N w=w*2 l=ln as=1.5u*w*2 ad=1.5u*w*2 ps=3u+w*2 pd=3u+w*2 m=mult region=sat
	pAParallel(int5 inA vDD vDD) ami06P w=w*4 l=lp as=1.5u*w*4 ad=1.5u*w*4 ps=3u+w*4 pd=3u+w*4 m=mult region=sat
	pBParallel(int5 inB vDD vDD) ami06P w=w*4 l=lp as=1.5u*w*4 ad=1.5u*w*4 ps=3u+w*4 pd=3u+w*4 m=mult region=sat
	pCiParallel(int5 carryIn vDD vDD) ami06P w=w*4 l=lp as=1.5u*w*4 ad=1.5u*w*4 ps=3u+w*4 pd=3u+w*4 m=mult region=sat
	pInvertedCarryOut(invertedSum invertedCarryOut int5 vDD) ami06P w=w*4 l=lp as=1.5u*w*4 ad=1.5u*w*4 ps=3u+w*4 pd=3u+w*4 m=mult region=sat
	nInvertedCarryOut(invertedSum invertedCarryOut int6 vSS) ami06N w=w*2 l=ln as=1.5u*w*2 ad=1.5u*w*2 ps=3u+w*2 pd=3u+w*2 m=mult region=sat
	nAParallel(int6 inA vSS vSS) ami06N w=w*2 l=ln as=1.5u*w*2 ad=1.5u*w*2 ps=3u+w*2 pd=3u+w*2 m=mult region=sat
	nBParallel(int6 inB vSS vSS) ami06N w=w*2 l=ln as=1.5u*w*2 ad=1.5u*w*2 ps=3u+w*2 pd=3u+w*2 m=mult region=sat
	nCiParallel(int6 carryIn vSS vSS) ami06N w=w*2 l=ln as=1.5u*w*2 ad=1.5u*w*2 ps=3u+w*2 pd=3u+w*2 m=mult region=sat
	pASeries(int7 inA vDD vDD) ami06P w=w*6 l=lp as=1.5u*w*6 ad=1.5u*w*6 ps=3u+w*6 pd=3u+w*6 m=mult region=sat
	pBSeries(int8 inB int7 vDD) ami06P w=w*6 l=lp as=1.5u*w*6 ad=1.5u*w*6 ps=3u+w*6 pd=3u+w*6 m=mult region=sat
	pCiSeries(invertedSum carryIn int8 vDD) ami06P w=w*6 l=lp as=1.5u*w*6 ad=1.5u*w*6 ps=3u+w*6 pd=3u+w*6 m=mult region=sat		
	nCiSeries(invertedSum carryIn int9 vSS) ami06N w=w*3 l=ln as=1.5u*w*3 ad=1.5u*w*3 ps=3u+w*3 pd=3u+w*3 m=mult region=sat
	nASeries(int9 inA int10 vSS) ami06N w=w*3 l=ln as=1.5u*w*3 ad=1.5u*w*3 ps=3u+w*3 pd=3u+w*3 m=mult region=sat
	nBSeries(int10 inB vSS vSS) ami06N w=w*3 l=ln as=1.5u*w*3 ad=1.5u*w*3 ps=3u+w*3 pd=3u+w*3 m=mult region=sat
ends mirrorAdder1Bit

//implement full adder on page 567 of book (Figure 11-6)
subckt mirrorAdder1Bit_NOTSIZEDCORRECTLY VDD VSS inA inB carryIn invertedSum invertedCarryOut
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1 widthMult=1
	pKillAParallel (int1 inA VDD VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	pKillBParallel (int1 inB VDD VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	pKillCi (invertedCarryOut carryIn int1 VDD) ami06P w=wp*widthMult l=lp  as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	pKillBSeries (int2 inB VDD VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	pKillASeries (invertedCarryOut inA int2 VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	nGenCi (invertedCarryOut carryIn int3 VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	nGenAParallel (int3 inA VSS VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	nGenBParallel (int3 inB VSS VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	nGenASeries (invertedCarryOut inA int4 VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	nGenBSeries (int4 inB VSS VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	pAParallel(int5 inA VDD VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	pBParallel(int5 inB VDD VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	pCiParallel(int5 carryIn VDD VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	pInvertedCarryOut(invertedSum invertedCarryOut int5 VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	nInvertedCarryOut(invertedSum invertedCarryOut int6 VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	nAParallel(int6 inA VSS VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	nBParallel(int6 inB VSS VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	nCiParallel(int6 carryIn VSS VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	pASeries(int7 inA VDD VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	pBSeries(int8 inB int7 VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat
	pCiSeries(invertedSum carryIn int8 VDD) ami06P w=wp*widthMult l=lp as=1.5u*wp*widthMult ad=1.5u*wp*widthMult ps=3u+wp*widthMult pd=3u+wp*widthMult m=mult region=sat		
	nCiSeries(invertedSum carryIn int9 VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	nASeries(int9 inA int10 VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
	nBSeries(int10 inB VSS VSS) ami06N w=wn*widthMult l=ln as=1.5u*wn*widthMult ad=1.5u*wn*widthMult ps=3u+wn*widthMult pd=3u+wn*widthMult m=mult region=sat
ends mirrorAdder1Bit_NOTSIZEDCORRECTLY
//
//7 TO 1 MUX (USING 2 TO 1 MUX AND 6 TO 1 MUX)
//
subckt mux7To1 VDD VSS in0 in1 in2 in3 in4 in5 in6 s0 s1 s2 out
inverterS0 (VDD VSS s0 sNOT0) ece3663Inverter
inverterS1 (VDD VSS s1 sNOT1) ece3663Inverter
inverterS2 (VDD VSS s2 sNOT2) ece3663Inverter
nandG1 (VDD VSS in1 sNOT0 sNOT1 sNOT2 out1) nand4  
nandG2 (VDD VSS in2 s0    sNOT1 sNOT2 out2) nand4
nandG3 (VDD VSS in3 sNOT0 sNOT1 s2    out3) nand4
nandG4 (VDD VSS in4 s0    sNOT1 s2    out4) nand4
nandG5 (VDD VSS in5 sNOT0 s1    s2    out5) nand4 
nandG6 (VDD VSS in6 s0    s1    s2    out6) nand4
nandBig (VDD VSS out1 out2 out3 out4 out5 out6 mux6To1Out) nand6
norControl (VDD VSS s2 sNOT1 finalControl) ece3663NOR2
mux2To1Final (VDD VSS mux6To1Out in0 finalControl out) ece3663MUX2to1
ends mux7To1

subckt nand6 VDD VSS in0 in1 in2 in3 in4 in5 out
p0 (out in0 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p1 (out in1 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p2 (out in2 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p3 (out in3 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p4 (out in4 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult
p5 (out in5 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult
n0 (out in0 inter1 VSS) ami06N w=6*wn l=ln as=1.5u*6*wn ad=1.5u*6*wn ps=3u+6*wn pd=3u+6*wn m=mult
n1 (inter1 in1 inter2 VSS) ami06N w=6*wn l=ln as=1.5u*6*wn ad=1.5u*6*wn ps=3u+6*wn pd=3u+6*wn m=mult
n2 (inter2 in2 inter3 VSS) ami06N w=6*wn l=ln as=1.5u*6*wn ad=1.5u*6*wn ps=3u+6*wn pd=3u+6*wn m=mult
n3 (inter3 in3 inter4 VSS) ami06N w=6*wn l=ln as=1.5u*6*wn ad=1.5u*6*wn ps=3u+6*wn pd=3u+6*wn m=mult
n4 (inter4 in4 inter5 VSS) ami06N w=6*wn l=ln as=1.5u*6*wn ad=1.5u*6*wn ps=3u+6*wn pd=3u+6*wn m=mult
n5 (inter5 in5 VSS VSS) ami06N w=6*wn l=ln as=1.5u*6*wn ad=1.5u*6*wn ps=3u+6*wn pd=3u+6*wn m=mult
ends nand6

subckt nand4 VDD VSS in0 in1 in2 in3 out
p0 (out in0 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p1 (out in1 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p2 (out in2 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p3 (out in3 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
n0 (out in0 inter1 VSS) ami06N w=4*wn l=ln as=1.5u*4*wn ad=1.5u*4*wn ps=3u+4*wn pd=3u+4*wn m=mult
n1 (inter1 in1 inter2 VSS) ami06N w=4*wn l=ln as=1.5u*4*wn ad=1.5u*4*wn ps=3u+4*wn pd=3u+4*wn m=mult
n2 (inter2 in2 inter3 VSS) ami06N w=4*wn l=ln as=1.5u*4*wn ad=1.5u*4*wn ps=3u+4*wn pd=3u+4*wn m=mult
n3 (inter3 in3 VSS VSS) ami06N w=4*wn l=ln as=1.5u*4*wn ad=1.5u*4*wn ps=3u+4*wn pd=3u+4*wn m=mult
ends nand4
//
//8 TO 1 MUX (USING 2 TO 1 MUXES)
//
subckt mux8To1FirstWay VDD VSS in0 in1 in2 in3 in4 in5 in6 in7 s0 s1 s2 out
//ece3663MUX2to1 VDD VSS in0 in1 Select out
mux000And001 (VDD VSS in0 in1 s0 out00) ece3663MUX2to1 
mux010And011 (VDD VSS in2 in3 s0 out01) ece3663MUX2to1
mux100And101 (VDD VSS in4 in5 s0 out10) ece3663MUX2to1
mux110And111 (VDD VSS in6 in7 s0 out11) ece3663MUX2to1
mux0 (VDD VSS out00 out01 s1 out0) ece3663MUX2to1
mux1 (VDD VSS out10 out11 s1 out1) ece3663MUX2to1
muxFinal (VDD VSS out0 out1 s2 out) ece3663MUX2to1
ends mux8To1FirstWay
//
//8 TO 1 MUX (USING 4-INPUT NAND GATES AND 8-INPUT NAND GATE)
//
subckt mux8To1SecondWay VDD VSS in0 in1 in2 in3 in4 in5 in6 in7 s0 s1 s2 out
inverterS0 (VDD VSS s0 sNOT0) ece3663Inverter
inverterS1 (VDD VSS s1 sNOT1) ece3663Inverter
inverterS2 (VDD VSS s2 sNOT2) ece3663Inverter
nandG0 (VDD VSS in0 sNOT0 sNOT1 sNOT2 out0) nand4  
nandG1 (VDD VSS in1 s0    sNOT1 sNOT2 out1) nand4
nandG2 (VDD VSS in2 sNOT0 s1    sNOT2 out2) nand4
nandG3 (VDD VSS in3 s0    s1    sNOT2 out3) nand4
nandG4 (VDD VSS in4 sNOT0 sNOT1 s2    out4) nand4 
nandG5 (VDD VSS in5 s0    sNOT1 s2    out5) nand4
nandG6 (VDD VSS in6 sNOT0 s1    s2    out6) nand4
nandG7 (VDD VSS in7 s0    s1    s2    out7) nand4
nandFinal (VDD VSS out0 out1 out2 out3 out4 out5 out6 out7 out) nand8
ends mux8To1SecondWay

subckt nand8 VDD VSS in0 in1 in2 in3 in4 in5 in6 in7 out
p0 (out in0 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p1 (out in1 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p2 (out in2 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p3 (out in3 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult
p4 (out in4 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p5 (out in5 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p6 (out in6 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
p7 (out in7 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
n0 (out in0 inter1 VSS) ami06N w=8*wn l=ln as=1.5u*8*wn ad=1.5u*8*wn ps=3u+8*wn pd=3u+8*wn m=mult
n1 (inter1 in1 inter2 VSS) ami06N w=8*wn l=ln as=1.5u*8*wn ad=1.5u*8*wn ps=3u+8*wn pd=3u+8*wn m=mult
n2 (inter2 in2 inter3 vSS) ami06N w=8*wn l=ln as=1.5u*8*wn ad=1.5u*8*wn ps=3u+8*wn pd=3u+8*wn m=mult
n3 (inter3 in3 inter4 VSS) ami06N w=8*wn l=ln as=1.5u*8*wn ad=1.5u*8*wn ps=3u+8*wn pd=3u+8*wn m=mult
n4 (inter4 in4 inter5 VSS) ami06N w=8*wn l=ln as=1.5u*8*wn ad=1.5u*8*wn ps=3u+8*wn pd=3u+8*wn m=mult
n5 (inter5 in5 inter6 VSS) ami06N w=8*wn l=ln as=1.5u*8*wn ad=1.5u*8*wn ps=3u+8*wn pd=3u+8*wn m=mult
n6 (inter6 in6 inter7 vSS) ami06N w=8*wn l=ln as=1.5u*8*wn ad=1.5u*8*wn ps=3u+8*wn pd=3u+8*wn m=mult
n7 (inter7 in7 VSS VSS) ami06N w=8*wn l=ln as=1.5u*8*wn ad=1.5u*8*wn ps=3u+8*wn pd=3u+8*wn m=mult
ends nand8
//
//REGISTER
//
subckt register16Bit VDD VSS clock in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 in15 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15   
parameters wpGlobal=3u wnGlobal=1.5u lnGlobal=600n lpGlobal=600n multGlobal=1
register0 (VDD VSS in0 clock out0) register1Bit
register1 (VDD VSS in1 clock out1) register1Bit
register2 (VDD VSS in2 clock out2) register1Bit
register3 (VDD VSS in3 clock out3) register1Bit
register4 (VDD VSS in4 clock out4) register1Bit
register5 (VDD VSS in5 clock out5) register1Bit
register6 (VDD VSS in6 clock out6) register1Bit
register7 (VDD VSS in7 clock out7) register1Bit
register8 (VDD VSS in8 clock out8) register1Bit
register9 (VDD VSS in9 clock out9) register1Bit
register10 (VDD VSS in10 clock out10) register1Bit
register11 (VDD VSS in11 clock out11) register1Bit
register12 (VDD VSS in12 clock out12) register1Bit
register13 (VDD VSS in13 clock out13) register1Bit
register14 (VDD VSS in14 clock out14) register1Bit
register15 (VDD VSS in15 clock out15) register1Bit
ends register16Bit

subckt register1Bit VDD VSS in externalClock out 
parameters wpGlobal=3u wnGlobal=1.5u lnGlobal=600n lpGlobal=600n multGlobal=1
inverterExternalClock1 (VDD VSS externalClock intermediate0) ece3663Inverter wp=wpGlobal wn=wnGlobal
inverterExternalClock2 (VDD VSS intermediate0 clock) ece3663Inverter wp=wpGlobal*2 wn=wnGlobal*2
inverterForNotClock (VDD VSS externalClock notClock) ece3663Inverter wp=wpGlobal wn=wnGlobal
//1st latch
//1st tgate
pTgate1 (in clock inter1 VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal 
nTgate1 (in notClock inter1 VSS) ami06N w=wnGlobal l=lnGlobal as=1.5u*wnGlobal ad=1.5u*wnGlobal ps=3u+wnGlobal pd=3u+wnGlobal m=multGlobal
//1st inverter
nInverter1 (inter2 inter1 VSS VSS) ami06N w=wnGlobal l=lnGlobal as=1.5u*wnGlobal ad=1.5u*wnGlobal ps=3u+wnGlobal pd=3u+wnGlobal m=multGlobal
pInverter1 (inter2 inter1 VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal 
//2nd inverter
nInverter2 (inter3 inter2 VSS VSS) ami06N w=wnGlobal l=lnGlobal as=1.5u*wnGlobal ad=1.5u*wnGlobal ps=3u+wnGlobal pd=3u+wnGlobal m=multGlobal
pInverter2 (inter3 inter2 VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal   
//2nd tgate
pTgate2 (inter3 notClock inter1 VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal 
nTgate2 (inter3 clock inter1 VSS) ami06N w=wnGlobal l=lnGlobal as=1.5u*wnGlobal ad=1.5u*wnGlobal ps=3u+wnGlobal pd=3u+wnGlobal m=multGlobal
//
//2nd latch
//1st tgate
pTgate3 (inter2 notClock inter4 VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal 
nTgate3 (inter2 clock inter4 VSS) ami06N w=wnGlobal l=lnGlobal as=1.5u*wnGlobal ad=1.5u*wnGlobal ps=3u+wnGlobal pd=3u+wnGlobal m=multGlobal
//1st inverter
nInverter3 (out inter4 VSS VSS) ami06N w=wnGlobal l=lnGlobal as=1.5u*wnGlobal ad=1.5u*wnGlobal ps=3u+wnGlobal pd=3u+wnGlobal m=multGlobal
pInverter3 (out inter4 VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal 
//2nd inverter
nInverter4 (inter5 out VSS VSS) ami06N w=wnGlobal l=lnGlobal as=1.5u*wnGlobal ad=1.5u*wnGlobal ps=3u+wnGlobal pd=3u+wnGlobal m=multGlobal
pInverter4 (inter5 out VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal   
//2nd tgate
pTgate4 (inter5 clock inter4 VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal 
nTgate4 (inter5 notClock inter4 VSS) ami06N w=wnGlobal l=lnGlobal as=1.5u*wnGlobal ad=1.5u*wnGlobal ps=3u+wnGlobal pd=3u+wnGlobal m=multGlobal
ends register1Bit
//
//SHIFTER TO BE INSERTED BELOW
//
subckt buffer VDD VSS in out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
	I0 (VDD VSS in temp) ccInverter
	I1 (VDD VSS temp out) ccInverter
ends buffer

subckt bufferf16 VDD VSS in out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
	I0 (VDD VSS in temp) ccInverter wp=12u wn=6u
	I1 (VDD VSS temp out) ccInverter wp=48u wn=12u
ends bufferf16

subckt tgate VDD VSS in out pass
parameters wp=3u wn =1.5u ln=600n lp=600n mult=1
   I3 (VDD VSS pass pass_inv) ccInverter
   N0 (in pass out VSS) ami06N w=wn l=ln as=2.25e-12 ad=2.25e-12 ps=6u \
           pd=6u m=mult region=sat
   P0 (out pass_inv in VDD) ami06P w=wp l=lp as=4.5e-12 ad=4.5e-12 ps=9u \
           pd=9u m=mult region=sat
ends tgate

subckt tGateMux VDD VSS in0 in1 select out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
   I0 (VDD VSS in0 outtemp selectPrime) tgate mult=mult
   I1 (VDD VSS in1 outtemp select) tgate mult=mult
   B0 (VDD VSS outtemp out) buffer
   I2 (VDD VSS select selectPrime) ccInverter mult=mult
ends tGateMux

subckt mux4to1 in00 in01 in10 in11 out Select0 Select1 VDD VSS
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
   I0 (VDD VSS in00 in01 Select0 IOout) tGateMux mult=mult
   I1 (VDD VSS in10 in11 Select0 I1out) tGateMux mult=mult
   //Inv0 (VDD VSS IOout I0inv) ccInverter
   //Inv1 (VDD VSS I0inv A0) ccInverter wp=12u wn=6u
   //Inv2 (VDD VSS I1out I1inv) ccInverter
   //Inv3 (VDD VSS I1inv A1) ccInverter wp=12u wn=6u
   I2 (VDD VSS I0out I1out Select1 out) tGateMux mult=mult
ends mux4to1

subckt ece3663mux4to1_Altered in00 in01 in10 in11 Select0 Select1 out
VDD VSS
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
   I0 (VDD VSS in00 in01 Select0 I0out) ece3663MUX2to1 wn=wn wp=wp mult=mult
   
   I1 (VDD VSS in10 in11 Select0 I1out) ece3663MUX2to1 wn=wn wp=wp mult=mult
   
   I2 (VDD VSS I0out I1out Select1 out) ece3663MUX2to1 wn=wn wp=wp mult=mult
ends ece3663mux4to1

subckt ccShifter VDD VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B0 B1 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 
	B1 (VDD VSS VSS out0) bufferf16
	mux8 (A7 A6 A5 A4 S0 S1 out8 VDD VSS) ece3663mux4to1_Altered 
	mux9 (A8 A7 A6 A5 S0 S1 out9 VDD VSS) ece3663mux4to1_Altered 
	mux10 (A9 A8 A7 A6 S0 S1 out10 VDD VSS) ece3663mux4to1_Altered 
	mux11 (A10 A9 A8 A7 S0 S1 out11 VDD VSS) ece3663mux4to1_Altered 
	mux15 (A14 A13 A12 A11 S0 S1 out15 VDD VSS) ece3663mux4to1_Altered 
	mux14 (A13 A12 A11 A10 S0 S1 out14 VDD VSS) ece3663mux4to1_Altered 
	mux13 (A12 A11 A10 A9 S0 S1 out13 VDD VSS) ece3663mux4to1_Altered 
	mux12 (A11 A10 A9 A8 S0 S1 out12 VDD VSS) ece3663mux4to1_Altered 
	mux4 (A3 A2 A1 A0 S0 S1 out4 VDD VSS) ece3663mux4to1_Altered 
	mux5 (A4 A3 A2 A1 S0 S1 out5 VDD VSS) ece3663mux4to1_Altered 
	mux6 (A5 A4 A3 A2 S0 S1 out6 VDD VSS) ece3663mux4to1_Altered 
	mux7 (A6 A5 A4 A3 S0 S1 out7 VDD VSS) ece3663mux4to1_Altered 
	mux3 (A2 A1 A0 VSS S0 S1 out3 VDD VSS) ece3663mux4to1_Altered 
	mux1 (A0 VSS VSS VSS S0 S1 out1 VDD VSS) ece3663mux4to1_Altered 
	mux2 (A1 A0 VSS VSS S0 S1 out2 VDD VSS) ece3663mux4to1_Altered 
	I0 (VDD VSS B0 invB0) ece3663Inverter
	I1 (VDD VSS invB0 S0) ece3663Inverter wp=12u wn=6u
	I2 (VDD VSS B1 invB1) ece3663Inverter
	I3 (VDD VSS invB1 B1t) ece3663Inverter
	I4 (VDD VSS B1t invB1t) ece3663Inverter
	I5 (VDD VSS invB1t S1) ece3663Inverter wp=6u wn=3u
	//S0 1,4
	//S1 1,1,1,2
ends ccShifter	
// End of subcircuit definition.
//
//COUNTER TO BE INSERTED BELOW
//subckt fullCounter VDD VSS s0 s1 s2 a0 a1 a2 clock out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15
xorCounterControl0 (VDD VSS s0 VDD s0NotEqualsCounterControl0) ece3663XOR2
xorCounterControl1 (VDD VSS s1 VDD s1NotEqualsCounterControl1) ece3663XOR2
xorCounterControl2 (VDD VSS s2 VDD s2NotEqualsCounterControl2) ece3663XOR2
orNotClear (VDD VSS s0NotEqualsCounterControl0 s1NotEqualsCounterControl1 s2NotEqualsCounterControl2 notClear) ece3663OR3
xorHeldS0 (VDD VSS s0 heldS0 s0NotEqualsHeldS0) ece3663XOR2
xorHeldS1 (VDD VSS s1 heldS1 s1NotEqualsHeldS1) ece3663XOR2
xorHeldS2 (VDD VSS s2 heldS2 s2NotEqualsHeldS2) ece3663XOR2
norCount (VDD VSS s0NotEqualsHeldSo s1NotEqualsHeldS1 s2NotEqualsHeldS2 count) ece3663NOR3
mux0 (VDD VSS a0 heldS0 notClear outMUX0) ece3663MUX2to1
mux1 (VDD VSS a1 heldS1 notClear outMUX1) ece3663MUX2to1
mux2 (VDD VSS a2 heldS2 notClear outMUX2) ece3663MUX2to1
registerHeldS0 (VDD VSS outMUX0 clock heldS0) register1Bit
registerHeldS1 (VDD VSS outMUX1 clock heldS1) register1Bit
registerHeldS2 (VDD VSS outMUX2 clock heldS2) register1Bit
counter0  (VDD VSS notClear count VSS   VDD   clock dIn0  out0)  counter1Bit
counter1  (VDD VSS notClear count dIn0  out0  clock dIn1  out1)  counter1Bit
counter2  (VDD VSS notClear count dIn1  out1  clock dIn2  out2)  counter1Bit
counter3  (VDD VSS notClear count dIn2  out2  clock dIn3  out3)  counter1Bit
counter4  (VDD VSS notClear count dIn3  out3  clock dIn4  out4)  counter1Bit
counter5  (VDD VSS notClear count dIn4  out4  clock dIn5  out5)  counter1Bit
counter6  (VDD VSS notClear count dIn5  out5  clock dIn6  out6)  counter1Bit
counter7  (VDD VSS notClear count dIn6  out6  clock dIn7  out7)  counter1Bit
counter8  (VDD VSS notClear count dIn7  out7  clock dIn8  out8)  counter1Bit
counter9  (VDD VSS notClear count dIn8  out8  clock dIn9  out9)  counter1Bit
counter10 (VDD VSS notClear count dIn9  out9  clock dIn10 out10) counter1Bit
counter11 (VDD VSS notClear count dIn10 out10 clock dIn11 out11) counter1Bit
counter12 (VDD VSS notClear count dIn11 out11 clock dIn12 out12) counter1Bit
counter13 (VDD VSS notClear count dIn12 out12 clock dIn13 out13) counter1Bit
counter14 (VDD VSS notClear count dIn13 out13 clock dIn14 out14) counter1Bit
counter15 (VDD VSS notClear count dIn14 out14 clock dIn15 out15) counter1Bit
ends fullCounter

subckt counter1Bit VDD VSS notClear count dPrevious outPrevious clock dIn out
inverterDPrevious (VDD VSS dPrevious dPreviousNOT) ece3663Inverter
outInverter (VDD VSS out outNOT) ece3663Inverter
dInAnd3 (VDD VSS outNOT dPreviousNOT outPrevious dIn) ece3663AND3
flipFlop (VDD VSS dIn clock out) register1Bit
ends counter1Bit
                                                                                                       /  >  F    	   	  o	  p	  s	  u	  v	  y	  {	  |	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  	  ͽͭwwwwwwwwwwww    $h h:m CJ OJ PJ  QJ ^J aJ  h:m CJ OJ PJ  QJ ^J aJ  $h hc CJ OJ PJ  QJ ^J aJ  hc CJ OJ PJ  QJ ^J aJ  h(d CJ OJ PJ  QJ ^J aJ  hs2 CJ OJ PJ  QJ ^J aJ  hQ CJ OJ PJ  QJ ^J aJ  $hQ hQ CJ OJ PJ  QJ ^J aJ .       ,  /   	  	  *
  k
  
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  T
  
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2 (
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2 (
Px4 #\'*.25@9                a$ gdQ  	  	  	  	  	  	  	  	  	  	  	  	  	  y      -  0  1  >  ?  I  J  a  b  t  u  w  x                              !  "  ,  -  C  D  V  W  Y  Z                                ݺݺ hma CJ OJ PJ  QJ ^J aJ  hc CJ OJ PJ  QJ ^J aJ  $h h:m CJ OJ PJ  QJ ^J aJ  $h hc CJ OJ PJ  QJ ^J aJ  h:m CJ OJ PJ  QJ ^J aJ C
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 CJ OJ PJ  QJ ^J aJ  h CJ OJ PJ  QJ ^J aJ  $h hgs CJ OJ PJ  QJ ^J aJ  hgs CJ OJ PJ  QJ ^J aJ  hA CJ OJ PJ  QJ ^J aJ  $h ht; CJ OJ PJ  QJ ^J aJ  ht; CJ OJ PJ  QJ ^J aJ 4j#  #  #  :$  ~$  $  %  T%  %  %  %&  n&  &  &  @'  '  %(  f(  (  (  )  H)  x)  )  )  **                                                                                                                                                                                                                                                                                                                           "  $ 
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2 (
Px4 #\'*.25@9                a$ gdgs  b1  c1  f1  s1  v1  2  3  95  p6  7   9  9  F:  :  ;  ;  ;  X<                                                                                                                                                                                                                           "  $ 
2 (
Px4 #\'*.25@9                a$ gdl "  $ 
2 (
Px4 #\'*.25@9                a$ gd "  $ 
2 (
Px4 #\'*.25@9                a$ gdQ  v1  42  2  7  7  7  C8  D8  N8  8  8  9  9  9  9  9  9  9  9  9  :  	:  
:  :  :  :  :  %:  &:  0:  1:  A:  B:  I:  J:  P:  Q:  Z:  b:  c:  h:  i:  r:  s:  t:  |:  }:  ʺ݊횊ww    $h hl CJ OJ PJ  QJ ^J aJ  hs2 CJ OJ PJ  QJ ^J aJ  hl CJ OJ PJ  QJ ^J aJ  h  CJ OJ PJ  QJ ^J aJ  h CJ OJ PJ  QJ ^J aJ  $h h CJ OJ PJ  QJ ^J aJ  hO| CJ OJ PJ  QJ ^J aJ  $h h CJ OJ PJ  QJ ^J aJ .}:  ~:  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  :  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ";  #;  $;  %;  .;  6;  7;  :;  ;;  <;  =;  E;  F;  G;  H;  P;  Q;  R;  S;  Y;  Z;  [;   hl CJ OJ PJ  QJ ^J aJ  hs2 CJ OJ PJ  QJ ^J aJ  $h hl CJ OJ PJ  QJ ^J aJ Q[;  \;  a;  b;  c;  d;  l;  m;  n;  o;  y;  z;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  <  <  	<  
<  <  <  <  <  <  <  <  <  <  $<  %<  &<  '<  -<  .<  /<  0<  5<  6<  7<  8<   hl CJ OJ PJ  QJ ^J aJ  $h hl CJ OJ PJ  QJ ^J aJ  hs2 CJ OJ PJ  QJ ^J aJ Q8<  @<  A<  B<  C<  M<  N<  S<  T<  W<  X<  [<  \<  `<  a<  b<  c<  l<  r<  s<  t<  u<  x<  y<  z<  {<  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  <  =  =  =  =  	=  
=  =  =  =   hl CJ OJ PJ  QJ ^J aJ  hs2 CJ OJ PJ  QJ ^J aJ  $h hl CJ OJ PJ  QJ ^J aJ QX<  <  ,=  =   >  k>  >  A?  ?  @  @  @  @  @  @  B  C  cD                                                                                                                                                                                                                           "  $ 
2 (
Px4 #\'*.25@9                a$ gd "  $ 
2 (
Px4 #\'*.25@9                a$ gd "  $ 
2 (
Px4 #\'*.25@9                a$ gdl  =  =  =  =  !=  "=  '=  (=  /=  0=  4=  5=  6=  7=  @=  F=  G=  H=  I=  L=  M=  N=  O=  W=  X=  Y=  Z=  b=  c=  d=  e=  k=  l=  m=  n=  s=  t=  u=  v=  ~=  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =  =   hl CJ OJ PJ  QJ ^J aJ  $h hl CJ OJ PJ  QJ ^J aJ  hs2 CJ OJ PJ  QJ ^J aJ Q=  =  =  =  =  =   >  >  >  >  	>  >  >  >   >  !>  +>  ,>  ->  6>  7>  ?>  @>  G>  H>  R>  S>  _>  `>  f>  g>  n>  o>  s>  t>  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  >  ?  ?  ?  ?  ?  ?  ?  ?  (?  *?  5?  7?  <?   hl CJ OJ PJ  QJ ^J aJ  hs2 CJ OJ PJ  QJ ^J aJ  $h hl CJ OJ PJ  QJ ^J aJ Q<?  =?  D?  E?  I?  K?  U?  \?  ]?  b?  c?  m?  n?  w?  y?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?  ?   @  @  
@  @  @  @  @  @  !@  +@  1@  3@  7@  9@  C@  D@  M@  N@  O@  V@  W@  X@  ^@  `@  i@  k@  v@  x@  }@  ~@  @                                 hs2 CJ OJ PJ  QJ ^J aJ  $h hl CJ OJ PJ  QJ ^J aJ  hl CJ OJ PJ  QJ ^J aJ K@  @  @  @  @  @  ^A  A  G  G  mG  nG  	H  H  -H  .H  4H  5H  >H  VH  WH  XH  bH  cH  kH  lH  sH  wH  xH  yH  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  H  I  I  I   I  (I  )I  *I  +I  ͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺͺ   $h h CJ OJ PJ  QJ ^J aJ  h CJ OJ PJ  QJ ^J aJ  h CJ OJ PJ  QJ ^J aJ  $h h CJ OJ PJ  QJ ^J aJ IcD  E  G  *H  H  H  VI  I  J  J  J  JK  K  L  vL  L  >M  M  N  jN  wN  xN                                                                                                                                                                                                                                                                           "  $ 
2 (
Px4 #\'*.25@9                a$ gd "  $ 
2 (
Px4 #\'*.25@9                a$ gd  +I  1I  2I  3I  4I  9I  :I  ;I  ?I  @I  AI  KI  LI  QI  RI  YI  ZI  ^I  _I  `I  aI  jI  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  I  J  J  J  J  J  	J  J  J  J  J  !J  "J  &J  'J  (J  )J  2J  JJ  KJ  LJ  TJ  UJ  VJ  WJ  ]J  ^J  _J     h CJ OJ PJ  QJ ^J aJ  $h h CJ OJ PJ  QJ ^J aJ W_J  `J  eJ  fJ  gJ  kJ  lJ  mJ  wJ  xJ  }J  ~J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  J  K  K  K  K  K  K  K  %K  &K  'K  (K  -K  .K  /K  3K  4K  5K  ?K  @K  EK  FK  MK  NK  RK  SK  TK  UK  ^K  vK  wK  xK  K  K  K  K  K  K  K  K     $h h CJ OJ PJ  QJ ^J aJ  h CJ OJ PJ  QJ ^J aJ WK  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  K  L  L  
L  L  L  L  L  L  L  L  &L  ?L  HL  IL  QL  RL  YL  ZL  \L  _L  jL  kL  qL  rL  yL  zL  ~L  L  L  L  L  L  L  L  L  L  L  L  L  L  L  L  L  L  L  L  L  M  M  M  M  M  !M     h CJ OJ PJ  QJ ^J aJ  $h h CJ OJ PJ  QJ ^J aJ W!M  #M  $M  'M  2M  4M  9M  :M  AM  BM  FM  HM  RM  kM  tM  vM  }M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  M  N  N  	N  
N  N  N  N  3N  <N  >N  EN  GN  MN  ON  PN  SN  ^N  `N  eN  fN  oN  sN  xN  zN  {N  N  ͺ                       $hQ h:; CJ OJ PJ  QJ ^J aJ  h:; CJ OJ PJ  QJ ^J aJ  $h h CJ OJ PJ  QJ ^J aJ  h CJ OJ PJ  QJ ^J aJ ExN  {N  N  N  :O  _O  O  O  O  O  P  =P  bP  P  P  P  P  Q  @Q  eQ  Q  Q                                                                                                                                                                                                                                                                           "  $ 
2 (
Px4 #\'*.25@9                a$ gd8
 "  $ 
2 (
Px4 #\'*.25@9                a$ gdQ  N  N  N  N  @O  AO  MO  NO  TO  UO  eO  fO  rO  sO  yO  zO  O  O  O  O  O  O  O  O  O  O  O  O  O  O  O  O  O  O  O  O  P  P  
P  P  P  P  +P  ,P  2P  3P  CP  DP  PP  QP  WP  XP  hP  iP  uP  vP  |P  }P  P  P  P  P  P  P  Q  Q  Q  Q  Q  ͽ  hjB CJ OJ PJ  QJ ^J aJ  h8
 CJ OJ PJ  QJ ^J aJ  $hQ h:; CJ OJ PJ  QJ ^J aJ  h:; CJ OJ PJ  QJ ^J aJ  hQ CJ OJ PJ  QJ ^J aJ DQ  Q  Q  Q  R  (R  +R  >R  AR  S  FS  pS  S  S  S  T  BT  lT                                                                                                                                                                                                                           "  $ 
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Px4 #\'*.25@9                a$ gd3 "  $ 
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2 (
Px4 #\'*.25@9                a$ gdQ  Q  Q  Q  Q  Q  Q  Q  R  	R  R  R  (R  *R  +R  AR  !S  "S  .S  /S  2S  3S  9S  :S  ES  KS  LS  XS  YS  \S  ]S  cS  dS  oS  uS  vS  S  S  S  S  S  S  S  S  S  S  S  𺪺ttt   $hQ h3 CJ OJ PJ  QJ ^J aJ  hC CJ OJ PJ  QJ ^J aJ  $ha
 h3 CJ OJ PJ  QJ ^J aJ  hQ CJ OJ PJ  QJ ^J aJ  h3 CJ OJ PJ  QJ ^J aJ  $hQ h:; CJ OJ PJ  QJ ^J aJ  $hQ h:; CJ OJ PJ  QJ ^J aJ  h:; CJ OJ PJ  QJ ^J aJ -S  S  S  S  S  S  S  S  S  S  S  S  S  S  S  S  S   T  T  T  T  T  T  T  T  T  *T  +T  .T  /T  5T  6T  AT  GT  HT  TT  UT  XT  YT  _T  `T  kT  qT  rT  ~T  T  T  T  T  T  T  T  T  T  T  T  T  T  T  T  T  T  U  U  2U  =U  \U  gU  U  U  U  U  U  U     h3 CJ OJ PJ  QJ ^J aJ  $hQ h3 CJ OJ PJ  QJ ^J aJ  hC CJ OJ PJ  QJ ^J aJ  $ha
 h3 CJ OJ PJ  QJ ^J aJ IlT  T  T  T  U  >U  hU  U  U  U  U  U  U  V  V  W  3W  [W                                                                                                                                                                                                                           "  $ 
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Px4 #\'*.25@9                a$ gdQ "  $ 
2 (
Px4 #\'*.25@9                a$ gd3  U  U  U  V  V  V  V  V  V  V  V  V  V  V  V  V  V  V  V   W  W  W  W  W   W  !W  'W  (W  7W  8W  DW  EW  HW  IW  OW  PW  _W  `W  lW  mW  pW  qW  wW  xW  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W  W   X  X  
X  X  X  X  X  'X  (X  4X  5X  8X  9X   h7 CJ OJ PJ  QJ ^J aJ  h)TE CJ OJ PJ  QJ ^J aJ  $ha
 h)TE CJ OJ PJ  QJ ^J aJ Q[W  W  W  W  W  #X  KX  sX  X  X  X  Y  ;Y  HY  KY  gY  jY  jZ  Z  Z  G[  [  [  I\  \  ]                                                                                                                                                                                                                                                                                                                   gdQ "  $ 
2 (
Px4 #\'*.25@9                a$ gd)TE  9X  ?X  @X  HY  jY  qY  ~Y  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  [  [  -[  /[  E[  G[  J[  K[  M[  N[  h[  s[  [  [  [  [  [  [  [  [  [  [  [  [  [  [  \  \  1\  G\  I\  L\  O\  P\  m\  x\  \  \  \  \  \  \  \  \  \   ]  ]  ]  ]  	]  ']      hVL  h}  hE8  hQ  h:;  h7 CJ OJ PJ  QJ ^J aJ  h)TE CJ OJ PJ  QJ ^J aJ P']  2]  G]  ]]  d]  v]  |]  }]  +^  =^  W^  X^  g^  h^  ^  ^  _  _  _  _  X_  Y_  [_  ]_  _  _  _  аzgWgzD  $hQ hq CJ OJ PJ  QJ ^J aJ  hVL CJ OJ PJ  QJ ^J aJ  $hq hq CJ OJ PJ  QJ ^J aJ  hq CJ OJ PJ  QJ ^J aJ  $hQ hE8 CJ OJ PJ  QJ ^J aJ  $hQ h CJ OJ PJ  QJ ^J aJ  hE8 CJ OJ PJ  QJ ^J aJ  h CJ OJ PJ  QJ ^J aJ  h. CJ OJ PJ  QJ ^J aJ  hQ CJ OJ PJ  QJ ^J aJ  hE8  hQ  hVL  h} ]  _]  |]  }]  ]  ]  +^  h^  ^  ^  _  _  Y_  _  _  _  %`  e`  z`  {`                                                                                                                                                                                                                                                                           "  $ 
2 (
Px4 #\'*.25@9                a$ gdE8 "  $ 
2 (
Px4 #\'*.25@9                a$ gdQ   gdQ  _  '`  )`  z`  {`  `  `  `  l  'l  (l  )l  xl  l  3|  T|  U|  |  |  |  |  X}  Y}  }  }  }  }  }  }  "~  #~  :~  =~  G~  H~  U~  V~  c~  d~  n~  q~  z~  {~  ~  A        +  A  ~~   hQ hx  h
@  hm  hQ  h)TE  hx  hB9  h	+  hB9 CJ OJ QJ ^J aJ   h(B hB9 CJ OJ QJ ^J aJ  hB9 CJ OJ PJ  QJ ^J aJ  h	+ CJ OJ PJ  QJ ^J aJ  hVL CJ OJ PJ  QJ ^J aJ  hq CJ OJ PJ  QJ ^J aJ 1{`  `  
a  a  a  }b  b  lc  c  Zd  d  Ie  e  'f  f  g  g  h  h  h  ki  i  Dj  j  8k                                                                                                                                                                                                                                                                                                                   $ a$ gdB9 "  $ 
2 (
Px4 #\'*.25@9                a$ gdB9  8k  k  l  (l  )l  bl  l  l  m  <n  n  o  0p  p  xq  r  r  ^s  s  t  4u  u  v  =w  w                                                                                                                                                                                                                                                                                                        gd	+ "  $ 
2 (
Px4 #\'*.25@9                a$ gdQ    $ a$ gdB9  w  xx  y  y  Sz  z  {  .|  U|  X|  |  |  |  |  &}  T}  }  }  }  ~  Q~  ~  ~  ~  A  N  O                                                                                                                                                                                                                                                                                                                                          gd
@   gdm   gdx   gdQ   gd	+  O      ,    ؀  -      I      x  ڃ        e      g  Ʌ  .           %                                                                                                                                                                                                                                                                                                                                               gdQ   gd
@   gd'   gdx  A      ׀    ,  0  B                      Á  ā  ́  ΁  ρ  ؁  ف  ځ        	  
        '  (  )  2  3  4  =  >  ?  H  _  `  d  m  n  o  x                          Â  ɂ  ҂  ӂ  Ԃ                        	      )  *  .  7  8  9  B  I  J  V   hm  hQ h'  h'  hx  hQ hx [V  W  a  b  f  l  m  n  w                      Ã  ă  Ń  ΃  σ  Ѓ  ك  ڃ      $  d  z    Є    &  f                        ȅ                    "  $  -  I  R  T  ]                Ɔ  Ȇ  ӆ  Ն  ކ                 ;  >  v    h>  h)TE  hx  hQ h
@  h
@  hQ h'  h'  hm V%  (  t    ؇    F  }        )  ,  j  m        D  x    ܊    A  s    ׋    3                                                                                                                                                                                                                                                                                                                                                              gdjB   gdQ  v          և  ۇ      E  I  |                  (  )  w  x  H  I  i  n  |  }          ϊ  Ԋ                  ?  E  F  G  r  w  x  y          ֋  ׋  4      ،    .  n    Í  ٍ    /  o    Ŏ  ێ    4  =  >  ?  O  P  h9W  hQ hC
  hC
  hv  hUS  h
@  hx  hjB  hN  h>  h)TE  hQ h)TE P3  4  m  Ì    o  č    p  Ǝ    ~    H      w  ܑ  >  I  L  W  Z    j    ʓ    *                                                                                                                                                                                                                                                                                                                                                    gd8t&   gdC
   gdQ  P  Q  \  ]  ^  g  h  i  r  s  t  }                    Ï  ̏  ͏  Ώ  ׏  ؏  ُ          	        &  '  1  2  6  <  =  >  G  c  l  m  n  ~                          Ȑ  ѐ  Ґ  Ӑ                                -  6  7  8  H  I  J  U  V  W  `  a  b  k  l     h9W  hQ hC
  hC
 _l  m  v  x  y                            ő  Ƒ  ʑ  Б  ё  ґ  ۑ  ݑ  ޑ                              '  (  )  2  3  4  =  >  I  K  L      ϖ  Ֆ  ۖ              
    \  t    Ǘ  ˗  ՗  ֗  ޗ          2  r  z  }                  Ř  Ș      h+T  h%5  h8t&  h9W  hQ hC
  hC
 Z*  Z          J  }        I  |          u  ֗  3  ?  K  Ԙ  _  n        %                                                                                                                                                                                                                                                                                                                                                                     gd8t&  Ș  Ҙ      	      "  +  3  :  B  I  Q  T  ^              Ǚ  ϙ  ֙  ޙ          '  /  2  :  C  K  T  \  c  k  r  z  }    Ě  ̚  Ϛ  ך                     $  Q  Y  \  d  m  u  ~                              $  +  3  :  B  E  O  |                    ǜ  Ϝ  Ҝ    h8t&  h+T b    Q  ݜ            #    8  G  џ  ^  j              ڡ  
                                                                                                                                                                                                                                                                                                   $ a$ gdw "  $ 
2 (
Px4 #\'*.25@9                a$ gdQ   gdQ   gd8t&  Ҝ  ܜ  &  .  1  9  B  J  S  [  b  j  q  y  |          Ɲ  ϝ  ם              	    L  T  W  _  h  p  y                ֞  ޞ                  !  )  ,  6  p  x  {                  ß  Ɵ  П        
      '  /  6  >  E  M  P  Z                 ʠ  Ѡ  ٠          h8t&  h+T b    %  -  0  8  A  I  R  Z  a  i  p  x  {                )  *  1  2  g  h  n  ĩ  ũ  
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  hc*  h{  hF  h(  h  hz  hN1 hw OJ QJ ^J  hN1 h OJ QJ ^J  h OJ QJ ^J 1  ı    X    ʲ    @  {  ȳ    b      I                                                                                                                                                                                                                "  $ 
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   gd{                          ѳ  ҳ                  	      :  ;  <  =  @  A  B  C  L  M  N  O  R  S  U  V  a                              3  4  5  6  9  :  <  =              ааааааааааааа   hEV CJ OJ PJ  QJ ^J aJ  h7 CJ OJ PJ  QJ ^J aJ  h CJ OJ PJ  QJ ^J aJ  h~) CJ OJ PJ  QJ ^J aJ  h^R CJ OJ PJ  QJ ^J aJ E      ͵  ε  ϵ  е  ӵ  Ե  ֵ  ׵             !  #  $  g  h  i  j  m  n  p  q                	  O  P  U  V                  6  7  <  =  K  [  \  x            7                                               h7  h;*  h,i  h<  hc* CJ OJ PJ  QJ ^J aJ  hqe CJ OJ PJ  QJ ^J aJ  hEV CJ OJ PJ  QJ ^J aJ  h CJ OJ PJ  QJ ^J aJ =  0  }  ʶ    d      K  \  ]        a                                                                                                                                                                                                                                                                                                gd< "  $ 
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2 (
Px4 #\'*.25@9                a$ gd  2 1h:pyLO / =! " # $ %                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              b                                           6  6  6  6  6  6  6  6  6  v  v  v  v  v  v  v  v  v  6  6  6  6  6  6  >  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6     6  6     6  6  6  6  6  6  6  6     6  6  6  6  6  6  6  6  6  6  6  6  h  H  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6  6    6  2                     0  @  P  `  p                   2  (         0  @  P  `  p                      0  @  P  `  p                      0  @  P  `  p                      0  @  P  `  p                      0  @  P  `  p                      0  @  P  `  p      8  X        V  ~     PJ _HmH	nH	sH	tH	    F  ` F   L    N o r m a l      $a$ CJ _HaJ mH	sH	tH	                  D A  D         D e f a u l t   P a r a g r a p h   F o n t     R i  R       0 T a b l e   N o r m a l      4 
l 4   a      ( k  (  
      0 N o   L i s t          e@    Q 0 H T M L   P r e f o r m a t t e d   =  $ 
2 (
Px4 #\'*.25@9                a$   CJ OJ PJ  QJ ^J aJ \  \   Q 0 H T M L   P r e f o r m a t t e d   C h a r    CJ OJ PJ  QJ ^J aJ D Z@ D  w 0
 P l a i n   T e x t      CJ OJ PJ QJ aJ J  !J   w 0 P l a i n   T e x t   C h a r    CJ OJ PJ QJ aJ PK     !         [Content_Types].xmlj0Eжr(΢Iw},-j4	wP-t#bΙ{UTU^hd}㨫)*1P'	^W0)T9<l#$yi};~@(Hu*Dנz/0ǰ$X3aZ,D0j~3߶b~i>3\`?/[G\!-Rk.sԻ..a濭?   PK     ! ֧   6     _rels/.relsj0}Q%v/C/} (h"O
= C?hv=Ʌ%[xp{۵_Pѣ<1H0ORBdJE4b$q_6LR7`0̞O,En7Lib/Seе   PK     ! ky         theme/theme/themeManager.xmlM
 @}w7c(Ebˮ CAǠҟ7՛K
Y,
e.|,H,lxɴIsQ}#Ր ֵ+!,^$j=GW)E+&
8   PK     !   P     theme/theme/theme1.xmlYOo6w toc'vuر-MniP@I}úama[إ4:lЯGRX^6؊>$!)O^rC$y@/yH*񄴽)޵߻UDb`}"qۋJחX^)I`nEp)liV[]1M<OP6r=zgbIguSebORD۫qu	gZo~ٺlAplxpT0+[}`jzA V2Fi@qv֬5\|ʜ̭NleXdsjcs7f
W+Ն7`gȘJj|h(KD- 
dXiJ؇(x$(:;˹!I_TS1?E??ZBΪmU/?~xY'y5g&΋/ɋ>GMGeD3Vq%'#q$8K)fw9:ĵ
x}rxwr:\TZaG*y8IjbRc|XŻǿI
u3KGnD1NIBs
RuK>V.EL+M2#'fi~Vvl{u8zH
*:(W☕
~JTe\O*tHGHY }KNP*ݾ˦TѼ9/#A7qZ$*c?qUnwN%Oi4=3ڗP
1Pm\\9Mؓ2aD];Yt\[x]}Wr|]g-
eW
)6-rCSj
id	DЇAΜIqbJ#x꺃6k#ASh&ʌt(Q%p%m&]caSl=X\P1Mh9MVdDAaVB[݈fJíP|8քAV^f
Hn-"d>znǊ	ة>b&2vKyϼD:,AGm\nziÙ.uχYC6OMf3or$5NHT[XF64T,ќM0E)`#5XY`פ ;%1U٥m;R>QDDcpU'&LE/pm%]8firS4d7y\`JnίIR3U~7+׸#mqBiDi*L69mY&iHE=(K&N!V.KeLDĕ{D	vEꦚdeNƟe(MN9ߜR6&3(a/DUz<{ˊYȳV)9Z[4^n5!J?Q3eBoCMm<.vpIYfZY_p[=al-Y}Nc͙ŋ4vfavl'SA8|*u{-ߟ0%M07%<ҍ    PK     ! 
ѐ     '   theme/theme/_rels/themeManager.xml.relsM
0wooӺ&݈Э5
6?$Q
,.aic21h:qm@RN;d`o7gK(M&$R(.1r'JЊT8V"AȻHu}|$b{ P8g/]QAsم(#L[    PK-      !                       [Content_Types].xmlPK-      ! ֧   6               +  _rels/.relsPK-      ! ky                     theme/theme/themeManager.xmlPK-      !   P                 theme/theme/theme1.xmlPK-      ! 
ѐ     '             	  theme/theme/_rels/themeManager.xml.relsPK      ]  
    <?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<a:clrMap xmlns:a="http://schemas.openxmlformats.org/drawingml/2006/main" bg1="lt1" tx1="dk1" bg2="lt2" tx2="dk2" accent1="accent1" accent2="accent2" accent3="accent3" accent4="accent4" accent5="accent5" accent6="accent6" hlink="hlink" folHlink="folHlink"/>        8      	    E    v1  }:  [;  8<  =  =  <?  @  +I  _J  K  !M  N  Q  S  U  9X  ']  _  A  V  v  P  l  Ș  Ҝ            ]   _   b   d   f   j   k   l   m   o   p   q   r   t   u   v   w   y   {   |   ~                                                
  y      j#  **  b1  X<  cD  xN  Q  lT  [W  ]  {`  8k  w  O  %  3  *    
            ^   `   a   c   e   g   h   i   n   s   x   z   }                                                  8                         @                           0    (    	                    
          B    
        S              	   ?              
            /   5   6   =          )           Y  [  a  c                  "  $  ,  .  g  i  o  q                  0  2  :  <  u  w  }                    >  @  H  J                  
        L  N  V  X                         "  ]  _  g  i                  2  4  :  <  w  y              	  	  	  	  L	  N	  T	  V	  	  	  	  	  	  	  	  	  
   
  (
  *
  f
  h
  n
  p
  y
  
                   o  q  w  y          Q
  S
  Y
  [
  
  
  
  
  3  5  ;  =                                  t  v  |  ~          b  d  j  l          P  R  X  Z  b  p                                         "  (  *  b  d  l  n                  .  0  6  8  p  r  z  |                  <  >  D  F  ~                        J  L  R  T                          X  Z  `  b                  $  &  .  0  l  n  t  v                  >  @  H  J                          X  Z  b  d                  -  /  5  7  @  I  T   V   \   ^               6!  8!  >!  @!  !  !  !  !  "  "   "  ""  "  "  "  "  "  "  #  #  k#  m#  s#  u#  #  #  #  #  M$  O$  U$  W$  $  $  $  $  ;%  =%  C%  E%  %  %  %  %  )&  +&  1&  3&  &  &  &  &  '  '  '  !'  )'  7'  (  (  (  (  (  (  U)  `)  v)  |)  *  *  *  *  p.  y.  2/  4/  /  /  0  0  1  1  8  8  8  8  9  :  :  :  =  =  \>  ^>  >  >   @  )@  oF  vF  F  F  I  I  AJ  GJ  M  M  jQ  pQ  R  R  lR  oR  pR  sR  tR  wR  xR  {R  |R  R  R  R  R  R  R  R  S  S  iS  sS  S  S  T  T  nT  xT  T  T  (U  2U  }U  U  U  U  CV  MV  V  V  W  W  {X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  Y  Y  Y   Y  #Y  $Y  'Y  (Y  +Y  =Y  ?Y  ZY  \Y  rY  vY  Y  Y  Y  Y  Y  Y  Y  Y  Y  Y  Y  Y  Y  Y  Y  Z  Z  Z  Z  Z  "Z  %Z  7Z  9Z  UZ  WZ  mZ  qZ  ~Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  Z  
[  [  [  [  [  +[  -[  F[  H[  \[  `[  m[  s[  u[  [  [  [  [  [  [  [  [  [  [  [  [  [  [   \  \  \  \  \  \  \  4\  6\  J\  N\  [\  h\  o\  r\  s\  v\  w\  z\  \  \  \  \  \  \  \  \  \  \  \  \  \  \  ]  
]  #]  %]  9]  =]  J]  U]  \]  _]  `]  c]  d]  g]  x]  z]  ]  ]  ]  ]  ]  ]  ]  ]  ]  ]  ]  ]  ]  ]  ^  ^  ^  ^  (^  2^  8^  ;^  <^  ?^  @^  C^  T^  V^  o^  q^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  	_  _  _  &_  '_  7_  =_  @_  Q_  S_  l_  n_  _  _  _  _  _  _  _  _  _  _  _  _  _  _  `  `  `  '`  -`  0`  1`  4`  5`  8`  I`  K`  d`  f`  z`  ~`  `  `  `  `  `  `  `  `  `  `  `  `  `  `  `  a  
a  a  a  a  a  a  *a  ,a  Ea  Ga  [a  _a  la  ta  za  }a  ~a  a  a  a  a  a  a  a  a  a  a  a  a  a  a  a  b  b  b   b  4b  8b  Eb  Nb  Ob  Zb  [b  bb  hb  kb  |b  ~b  b  b  b  b  b  b  b  b  b  b  b  b  b  b  c  c  (c  ,c  9c  Ac  Gc  Jc  Qc  Tc  ec  gc  c  c  c  c  c  c  c  c  c  c  c  c  c  c  c  c  d  d  bd  hd  d  d  d  d  d  d  d  d  d  d  d  d  d  d  d  d  d  d  d  d  d  d  d  e  e  e  e  e  (e  *e  +e  4e  7e  9e  Be  De  Ee  Ne  We  Ye  Ze  ce  de  fe  me  ve  e  e  e  e  e  e  e  e  e  e  e  e  e  e  e  e  e  e  e  e  e  e  e  f  f  f  
f  f   f  )f  ,f  0f  =f  Df  Ff  Vf  Wf  ^f  rf  tf  uf  ~f  f  f  f  f  f  f  f  f  f  f  f  f  f  f  f  f  f  f  f  f  f  f  g  g  g  g  g  g   g  "g  +g  -g  .g  7g  @g  Bg  Cg  Lg  Mg  Og  Vg  _g  ig  rg  ug  yg  g  g  g  g  g  g  g  g  g  g  g  g  g  g  g  g  g  g  g  g  g  g  h  
h  h  h   h  $h  1h  7h  9h  Ih  Jh  Qh  eh  gh  hh  qh  th  vh  h  h  h  h  h  h  h  h  h  h  h  h  h  h  h  h  h  h  h  h  h  h  i  i  i  i  i  i  i   i  !i  *i  3i  5i  6i  ?i  @i  Bi  Ii  Ri  \i  ei  hi  li  yi  i  i  i  i  i  i  i  i  i  i  i  i  i  i  i  i  i  i  i  i  i  i  i  i  j  j  j  j  #j  %j  5j  6j  9j  Mj  Oj  Pj  Yj  \j  ^j  gj  ij  jj  sj  |j  ~j  j  j  j  j  j  j  j  j  j  j  j  j  j  j  j  j  j  j  j  j  j  j  k  k  k  k  k  k  k  %k  &k  (k  /k  8k  Bk  Kk  Nk  Rk  _k  ik  ok  rk  wk  zk  k  k  k  k  k  k  k  k  k  k  k  k  k  k  k  k  k  k  k  k  k  k  k  l  
l  
l  l  l   l  "l  #l  ,l  /l  1l  :l  <l  =l  Fl  Ol  Ql  Rl  [l  \l  ^l  el  nl  xl  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  l  m  m  m  !m  $m  (m  5m  Fm  Gm  Rm  Sm  cm  wm  ym  zm  m  m  m  m  m  m  m  m  m  m  m  m  m  m  m  m  m  m  m  m  m  m  	n  
n  n  .n  0n  1n  :n  =n  ?n  Hn  Jn  Kn  Tn  ]n  _n  `n  in  jn  ln  sn  |n  n  n  n  n  n  n  n  n  n  n  n  n  n  n  n  n  n  n  n  n  n  n  n  o  o  o  o  o  !o  *o  -o  1o  >o  Ho  No  Qo  Vo  Yo  do  fo  go  po  so  uo  ~o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  p  p  p  p  p  p  p   p  !p  *p  3p  5p  6p  ?p  @p  Bp  Ip  Rp  \p  ep  hp  lp  yp  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  p  q  q  q  q   q  #q  7q  9q  :q  Cq  Fq  Hq  Qq  Sq  Tq  ]q  fq  hq  iq  rq  sq  uq  |q  q  q  q  q  q  q  q  q  q  q  q  q  q  q  q  q  q  q  q  q  r  r  r  r  r  r  r  "r  +r  5r  >r  Ar  Er  Tr  ]r  ^r  ir  jr  qr  r  r  r  r  r  r  r  r  r  r  r  r  r  r  r  r  r  r  r  r  r  r  r  s  s  s   s  "s  #s  ,s  /s  1s  :s  <s  =s  Fs  Os  Qs  Rs  [s  \s  ^s  es  ns  xs  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  s  t  t  t  t  "t  .t  Tt  t  t  v  v  v  v  v  v   w  ,w  Ow  Uw  w  w  w  w  w  w  w  w  w  w  w  w  w  w  w  w  w  w  w  w  x  x  x  x  x  x  &x  *x  <x  ?x  Jx  Lx  Ox  Qx  Zx  \x  ex  gx  hx  jx  |x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  y  y  y  y  y  y  (y  ,y  =y  @y  Ky  My  Py  Ry  [y  ]y  fy  hy  iy  ky  }y  y  y  y  y  y  y  y  y  y  y  y  y  y  y  y  y  y  
z  z  z  z  z  z  )z  +z  ,z  .z  4z  6z  ?z  Az  Dz  Hz  oz  qz  tz  vz  z  z  z  z  z  z  z  z  z  z  z  z  z  z  z  z  z  z  z  z  z  z  z   {  	{  {  {  {  9{  ;{  >{  @{  K{  M{  X{  Z{  [{  ]{  c{  e{  n{  p{  s{  w{  {  {  {  {  {  {  {  {  {  {  {  {  {  {  {  {  {  {  {  {  |  "|  -|  /|  2|  4|  =|  ?|  H|  J|  K|  M|  _|  c|  u|  x|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  }  }  !}  $}  /}  1}  4}  6}  ?}  A}  J}  L}  M}  O}  a}  e}  }  }  }  }  }  }  }  }  }  }  }  }  }  }  }  }  }  }  }  }  ~  ~  ~  ~  ~  ~  ~  ~  $~  &~  )~  -~  T~  V~  Y~  [~  f~  h~  s~  u~  v~  x~  ~~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~  (  .      m  s  ׃    4  :  }                            ӄ  ք                          )  ,  7  9  <  >  G  I  R  T  U  W  i  m                            Å  ԅ  ׅ                           *  -  8  :  =  ?  H  J  S  U  V  X  j  n                            Ć  ֆ  ن                          ?  A  D  F  Q  S  ^  `  a  c  i  k  t  v  y  }              Ç  Ň  Ƈ  ȇ  ·  Ї  ه  ۇ  އ        	            (  *  +  -  3  5  >  @  C  G  n  p  s  u                          ӈ  Ո  ؈  ڈ                    
  
    8  :  =  ?  J  L  W  Y  Z  \  b  d  m  o  r  v                          ǉ  ɉ  ҉  ԉ  ׉  ۉ                       !  #  )  +  4  6  9  =  Z  `  '  /  3  ;  A  I  O  W  ]  g          ͎  Վ  َ              
  0  =  ]  _  `  h  i  k  l  t        ŏ  ȏ  ʏ  ˏ  ӏ  ֏           	        &  '  )  *  2  E  J  r  z  }                Ȑ  Ґ          	      "  +  3  4  6  T  ^                  Ǒ  ϑ  Б  ґ          '  /  2  :  C  K  T  \  ]  _  }        Ē  ̒  ϒ  ג                $  C  F  Q  Y  \  d  m  u  ~                ѓ  ٓ                $  %  '  E  O  |                    Ҕ  ܔ          &  .  1  9  B  J  S  [  \  ^  |          ƕ  ϕ  ו          	    >  A  L  T  W  _  h  p  y            Ȗ  ˖  ֖  ޖ                  ,  6  b  e  p  x  {                Ɨ  З            
      '  /  0  2  P  Z  d  i                ʘ  ˘  ͘          %  -  0  8  A  I  R  Z  [  ]  {      Ù                         *  B  L  Z  `                        ʚ  ˚  ͚  Қ  Ԛ                    $  D  F  J  L  S  U  [  ]  c  g  ~                ԛ  ֛      
    $  &  )  +  B  D  ]  a  r  w  y                    Ŝ  ǜ  ͜  ќ                        &  /  4  5  9  :  >  N  U  x                                    	        9  >  @  H  I  M  N  R  {                    ֞                6  @  A  C  H  J  v  ~                                   L  N  O  Q  R  T  U  W  X  \  ]  a                                                         )  ҡ  ա  B  E  F  I                      ۦ        ,  2  3  >          ĩ  ̩  7  ?  p  x          ۫    (  0  u  }  ¬  ʬ      \  d          C  K      ݮ    *  2  w    į  ̯      P  [  ]  c  x                    ư  ϰ  а  ܰ        
  0  6  7  C  D  O  P  S  a  i  s  v                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    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  3  6                   t  w        3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3  3        -  b    c)  8  wF            =           3h           v]2            o!           HWj&           n(           X)           u*5           D*9           _<           <D           .uG           1S           <_V           *>Z           {^           :g           k}`h           
{           u                o   ;  q  N 7 
 C
 8
 i :m c] C  
 w VL 9$ 8t& ( ~) ;* c* g* @., o_2 s2 3 5 f6 E8 B9 t; 
@ jB )TE F yLO ^R +T EV 9W ZX Z (d ,i 1Li 8k Wm -v Zav $} &} cW D L u< K q; > '  l z { w \ :; x )` A   < qe ? W^ \ I  gs ` 	 [> 7 Q  z US C  } ma   i . m  % l \= Yb   v X c 
 %5 a
 Vn s 	5 n  ;] 	+ O|                @                                         @      U n k n o w n                                   G  * Ax 	             T i m e s   N e w   R o m a n   5                       S y m b o l   3.  * Cx 	             A r i a l   ?=  	* Cx 	             C o u r i e r   N e w   7.   {  @               C a l i b r i   9=  	 K  @               C o n s o l a s   A     B               C a m b r i a   M a t h   "  1   h    FF              Z    B       Z   B      !                                                                                                                                                                                                                                                                                                                           x  20    d      F  F                                                                        2                           HX    	$P        Q    2                     !                             x   x                             S t u d e n t  S t u d e n t                                                                                                                                                                                                                                                                                                                                                                                                                                             Oh +'0     
      p      x               	            
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                                                             !   "   #   $   %   &   '   (   )   *   +   ,   -   .   /   0   1   2   3   4   5   6   7   8   9   :   ;   <   =   >   ?   @   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   [   \   ]   ^   _   `   a   b   c   d   e   f   g   h   i   j   k   l   m   n   o   p   q   r   s   t   u   v   w   x   y   z   {   |   }   ~                                                                                                                                                                                                                                                                                                                        R o o t   E n t r y                                                 	           F            0          D a t a                                                         
                                               1 T a b l e                                                                                                 b      W o r d D o c u m e n t                                          
                                              48      S u m m a r y I n f o r m a t i o n                           (                                                D o c u m e n t S u m m a r y I n f o r m a t i o n           8                                                  M s o D a t a S t o r e                                                                  @0            D   2 E   T R  S I    E     T A = =                 2                        @0            I t e m                                                         
 	                                                  P r o p e r t i e s                                                                                      U       C o m p O b j                                                                                            
   y                                                                                                                                                	      <b:Sources SelectedStyle="\APA.XSL" StyleName="APA" xmlns:b="http://schemas.openxmlformats.org/officeDocument/2006/bibliography" xmlns="http://schemas.openxmlformats.org/officeDocument/2006/bibliography"></b:Sources>
                                      <?xml version="1.0" encoding="UTF-8" standalone="no"?>
<ds:datastoreItem ds:itemID="{125C090F-13DF-4446-88FB-1B44CECF344C}" xmlns:ds="http://schemas.openxmlformats.org/officeDocument/2006/customXml"><ds:schemaRefs><ds:schemaRef ds:uri="http://schemas.openxmlformats.org/officeDocument/2006/bibliography"/></ds:schemaRefs></ds:datastoreItem>                                            
  	           F'   Microsoft Office Word 97-2003 Document 
   MSWordDoc    Word.Document.8 9q                                                                                                                                                                                                                                                                                   